View TC6387XB_1322340.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TC6387XB Specification
Rev. 1.0 02/02/06
SD Memory Card / SDIO Card Controller
TC6387XB
Outline
Rev. 1.0 2002-02-06
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.1
TC6387XB Specification
Rev. 1.0 02/02/06
Revision History TITLE: TC6387XB Specifications REV NO. 0.90a 0.90b DATE 2001-08-17 2001-11-12 CONTENTS Released 1st edition *Modified SD Control Register Map again(page 16). *Regarding [4.7 SDLED signal], added the comments in detail(page 21). *Regarding [4.7 Clock supply to SD Card], added the comments in detail(page 21-22). *Added DC and AC specifications(page 26-40). *Regarding [4.1.2 Compact Flash (CF) Interface], defined that #STSCHG of CF interface is not connected to TC6380AF signal(page 13). *Added [Appendix](page42-46). Corrected the written(page14, red letters). Added each signal states in suspend mode(#SUSPEND=Low)(page24). Added an interrupt specification in detail(Page19-37). Regarding AC Characteristic, modified written max time to min time. Regarding Attribute Memory Interface AC Characteristic, added a specification of thoh8 (page 57). Regarding SD Card Interface AC Characteristic, modified a specification of Fpp (16MHz 25MHz) (Page 59). Deleted the function of CompactFlash Interface. Then, defined again HISEL signal as RSV2 signal. Deleted the function of SDICK. Then, defined again SDICK signal as RSV0 signal and CKSEL signal as RSV1 signal. Modified [4.5 Interruption]. Modified the recommended external resistances of #SDCD and SDWP signals. Added [6. Caution in coding device driver]. Added [B Reference diagram]. REVISED by S. Ueta S. Ueta APP'D by T. Takada T. Takada
0.90c
2001-11-21
S. Ueta
T. Takada
0.90d 0.90e 0.90f 0.90g
2001-11-27 2001-12-05 2001-12-20 2001-12-25
S. Ueta S. Ueta S. Ueta S. Ueta
T. Takada T. Takada T. Takada T. Takada
1.0
2002-02-06
S. Ueta
T. Takada
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.2
TC6387XB Specification
Rev. 1.0 02/02/06
Contents
1 Overview ____________________________________________________________________________________ 5 1.1 Chip Specifications_________________________________________________________________________ 5 1.2 Overview Specifications_____________________________________________________________________ 5 2 3 Block Diagram ______________________________________________________________________________ 6 Signals ____________________________________________________________________________________ 7 3.1 3.2 3.3 3.4 4 Pin Assignments________________________________________________________________________ 7 Pin Signals ______________________________________________________________________________ 8 Power Supply/GND (10 pins) ______________________________________________________________ 11 Summary: Interface Pins __________________________________________________________________ 11
Functionality Descriptions ____________________________________________________________________ 12 4.1 4.2 Host Interface __________________________________________________________________________ 12 Resource Area __________________________________________________________________________ 12
4.3 Register Map ___________________________________________________________________________ 14 4.3.1 SD Host Controller Configuration Register ________________________________________________ 14 4.3.2 SD Control Register __________________________________________________________________ 15 4.4 Clock/Reset ____________________________________________________________________________ 16 4.4.1 Clock _____________________________________________________________________________ 16 4.4.2 Reset-related items ____________________________________________________________________ 16 4.5 Interruption ____________________________________________________________________________ 4.5.1 SD card insertion interrupt by #SDCD _____________________________________________________ 4.5.2 SD card removal interrupt by #SDCD______________________________________________________ 4.5.3 Buffer write enable interrupt _____________________________________________________________ 4.5.4 Buffer read enable interrupt______________________________________________________________ 4.5.5 Response end interrupt _________________________________________________________________ 4.5.6 R/W end interrupt _____________________________________________________________________ 4.5.7 Illegal access error interrupt _____________________________________________________________ 4.5.8 Buffer underflow error interrupt __________________________________________________________ 4.5.9 Buffer overflow error interrupt ___________________________________________________________ 4.5.10 Time out error(command) interrupt_______________________________________________________ 4.5.11 Read data time out error interrupt ________________________________________________________ 4.5.12 Busy time out error interrupt ____________________________________________________________ 4.5.13 CRC status busy time out error interrupt___________________________________________________ 4.5.14 CRC status time out error interrupt _______________________________________________________ 4.5.15 End bit error interrupt _________________________________________________________________ 4.5.16 CRC error interrupt ___________________________________________________________________ 4.5.17 Command Index error interrupt__________________________________________________________ 4.5.18 Illegal function select interrupt __________________________________________________________ 4.5.19 SDIO Card interrupt __________________________________________________________________ 17 17 17 18 19 20 21 22 23 24 25 26 28 29 31 33 34 35 36 37
4.6 Card Slot Power Supply Control ____________________________________________________________ 38 4.6.1 SD Card Slot Power Supply Controller ___________________________________________________ 38 4.7 4.8 4.9 SDLED signal __________________________________________________________________________ 39 Clock supply to SD Card __________________________________________________________________ 39 Suspension_____________________________________________________________________________ 40
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.3
TC6387XB Specification
Rev. 1.0 02/02/06
4.10 Pull-up/down Resistance _________________________________________________________________ 4.10.1 Host Interface ______________________________________________________________________ 4.10.2 SD Card Interface ___________________________________________________________________ 4.10.3 System Interface ____________________________________________________________________ 4.11 5
42 42 42 42
Connection example of SD Card socket _____________________________________________________ 43
Electrical Characteristic ______________________________________________________________________ 44 5.1 Absolute Maximum Standard ______________________________________________________________ 44 44 44 45 46 46 47 47 48 49 49 53 54
5.2 DC Characteristic _______________________________________________________________________ 5.2.1 Recommended Conditions for proper performances _________________________________________ 5.2.2 Host Interface DC Characteristic ________________________________________________________ 5.2.3 SD Card Interface Pin DC Characteristic __________________________________________________ 5.2.4 SD Card Power Supply Control DC Characteristic __________________________________________ 5.2.5 System Interface Pin DC Characteristic ___________________________________________________ 5.2.6 TEST Pin DC Characteristic____________________________________________________________ 5.2.7 Power Consumption Characteristic ______________________________________________________ 5.3 AC Characteristic _______________________________________________________________________ 5.3.1 Host Interface Signal AC Characteristic___________________________________________________ 5.3.2 SD Card Interface Signal AC Characteristic _______________________________________________ 5.3.3 System Interface Signal AC Characteristic ________________________________________________ 6
Caution in coding device driver ________________________________________________________________ 55 6.1 6.2 Regarding a SD card insertion and removal ___________________________________________________ 55 Regarding controlling Stop Clock Control Register _____________________________________________ 55
7
Package outline_____________________________________________________________________________ 56
Appendix ____________________________________________________________________________________ 57 A TC6387XB function confirmation with standard memory interface ____________________________________ 57 A.1 A.2 A.3 A.4 B Sample soft for standard memory interface of TC6387XB _______________________________________ 57 Wait mode specification __________________________________________________________________ 58 The wiring image of 16bit internal wait mode _________________________________________________ 59 The wiring image of 16bit external wait mode _________________________________________________ 60
Reference diagram __________________________________________________________________________ 61
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.4
TC6387XB Specification
Rev. 1.0 02/02/06
1 Overview TC6387XB is a controller LSI for SD Memory Card/SDIO Card that comes in with interfaces for Standard Memory with 16 bits bus. Also, TC6387XB meets SD Memory Card Physical Layer Specification and SD I/O Card Specification. TC6387XB automatically detects card types and power supply just by inserting SD Memory Card or SDIO Card. By using buffer-off function of #SUSPEND signal and gated clock control, power consumption of the system can be kept to a minimum.
1.1 Chip Specifications - 0.35um CMOS Process - 0.8mm ball Pitch 64-pin FBGA Package (Body Size: 7mm 7mm) (Height : Max.1.2mm) 1.2 Overview Specifications - Host Bus Interface Standard Memory Interface 16 bit bus Interface - Interruption Support - Operating Frequency 33MHz - Compatible w/ Power Supply Control LSI MIC2563 - Supports SD Card 1 Slot - Meets SD Memory Card Physical Layer Specification Ver.1.0 Operating Frequency (Max. 25MHz) MultiMedia Card Read/Write Capability Compatible w/ 3.3V Compatible w/ Multi Block Write/Read Not compatible w/ SPI Mode Within 512Byte*2 Double Buffers - Meets SD I/O Card Specification Ver.1.0 Operating Frequency (Max. 25MHz) Compatible w/ 3.3V Compatible w/ Multi Block Write/Read
FBGA Package
Though Toshiba specified TC6387XB DC supply voltage range(3.0v < Vdd < 3.6v) as recommended commercial operating condition, SDIO card specification has different DC supply voltage range(3.1v < Vdd < 3.5v). Toshiba recommend DC supply voltage range(3.1v < Vdd < 3.5v) in case customer use a SDIO card with TC6387XB as recommended commercial operating condition.
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.5
TC6387XB Specification
Rev. 1.0 02/02/06
2
Block Diagram
System Bus
TC6387XB
Interrupt Control System Interface Control
SD Memory Card /SDIO Card Power Control Power Control SD Memory Card / SDIO Card Control Control Register
Power Switch
SD Memory Card / SDIO Card
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.6
TC6387XB Specification
Rev. 1.0 02/02/06
3 3.1
Signals Pin Assignments
Top View
1 A B C D E F G H CLK32 SDPWR VDD SDCLK SDCD0 SDLED #HINT HCLK
2 RSV0 VDD SDCD3 SDCMD #SDCD HRDY VDD VSS
3 TST1 TST2 SDCD2 SDCD1 SDWP #PCLR #HOE #HBEH
4 #SUSPEND RSV1 TST0 VSS VSS HD14 #HWE #HBEL
5 #HCS HA2 RSV2 VSS VSS HD12 HD13 HD15
6 HA1 HA3 HA4 HA10 HD0 HD6 HD10 HD11
7 HA5 VDD HA8 HA11 HD4 HD5 VDD HD9
8 HA6 HA7 HA9 HD1 HD2 HD3 HD7 HD8
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.7
TC6387XB Specification
Rev. 1.0 02/02/06
3.2
Pin Signals
Host Interface (33-pin) NAME HD15 HD14 HD13 HD12 HD11 HD10 HD9 HD8 HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 HA11 HA10 HA9 HA8 HA7 HA6 HA5 HA4 HA3 HA2 HA1 #HCS #HOE #HWE #HBEL #HBEH HRDY *1 Pin H5 F4 G5 F5 H6 G6 H7 H8 G8 F6 F7 E7 F8 E8 D8 E6 D7 D6 C8 C7 B8 A8 A7 C6 B6 B5 A6 A5 G3 G4 H4 H3 F2 IO VCC (V) FUNCTION/REMARKS System Data 15-0
IO
3.3
I I I I I I I I I I I I I I I I O (OD) *1
System Address 11-1
3.3
Chip Selection Output Enabled Write Enabled Byte Enabled L Byte Enabled H Ready
Levels cannot be converted.
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.8
TC6387XB Specification
Rev. 1.0 02/02/06
Pin Signals (cont'd) SD Card Interface (9-pin) NAME SDCD3 SDCD2 SDCD1 SDCD0 SDCMD SDCLK #SDCD SDWP SDLED Pin C2 C3 D3 E1 D2 D1 E2 E3 F1 IO VCC (V) FUNCTION/REMARKS
IO 3.3
SD Card /Data Bus
O I O
SD Card /Command SD Card /Divided HCLK Clock for SD Card(Max.25MHz) SD Card /Detection SD Card /Write Protection Media is write-protected when this Pin indicates "High". SD Card /LED signal
* Buffer with pull-up resistance
SD Card Power Supply Control (1-pin) NAME SDPWR Pin B1 IO O VCC (V) 3.3 FUNCTION/REMARKS SD Card Power Supply Control. 3.3V Enable Signal
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.9
TC6387XB Specification
Rev. 1.0 02/02/06
Pin Signals (cont'd) SYSTEM Interface (5-pin) NAME HCLK CLK32 #HINT #PCLR #SUSPEND *1 Pin H1 A1 G1 F3 A4 I O (OD) *1 I 3.3 IO VCC (V) FUNCTION/REMARKS System Clock (max.33MHz) Used for card detection and for interruption detection when HCLK is stopped. Interruption All registers are cleared when this signal is asserted Suspend
Levels cannot be converted.
TEST Pin (3-pin) NAME TST2 TST1 TST0 Pin B3 A3 C4 IO I VCC (V) 3.3 FUNCTION/REMARKS Test Mode Signal 2,1,0 Utilized for Test Mode Set "000" for TST[2-0] under normal circumstances.
Other Pin (3-pin) NAME RSV0 RSV1 RSV2 Pin A2 B4 C5 IO I VCC (V) 3.3 FUNCTION/REMARKS Link to directly ground. Link to directly ground. Link to directly ground.
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.10
TC6387XB Specification
Rev. 1.0 02/02/06
3.3
Power Supply/GND (10 pins) NAME VSS VDD H2, D4, E4, D5, E5 C1, B2, G2, B7, G7 Pin GND 3.3V FUNCTION/REMARKS
3.4
Summary: Interface Pins # of Pins 33 9 1 11 54 5 5 64 SYSTEM Interface, TEST Pins, Other Pins Remarks
Interface Host SD Card SD Card Power Supply Control System Total Power Supply GND Grand Total
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.11
TC6387XB Specification
Rev. 1.0 02/02/06
4 4.1
Functionality Descriptions Host Interface
TC6387XB supports standard memory interfaces and the following suggests examples of circuits for connecting to Standard Memory Interface: Standard Memory A11-1 D15-0 -CS -OE -WE -BEH -BEL -RDY TC6387XB HA11-1 HD15-0 #HCS #HOE #HWE #HBEH #HBEL HRDY
4.2
Resource Area
TC6387XB holds the following Resource Area: 1) SD Host Controller Configuration Area 2) SD Control Register Area See below for mapping of SD Host Controller Configuration Area and SD Control Register Area. Further, SD Control Register Area are mapped to any memory resources(800-FFFh) by setting BASE Address Register in SD Host Controller Configuration Area. Offset A11-1 000 - 0FFh 100 - 1FFh 200 - 2FFh 300 - 3FFh 400 - 7FFh 800 - 8FFh 900 - 9FFh A00 - AFFh B00 - BFFh C00 - FFFh FUNCTION/REMARKS Reserved for Configuration Area Reserved for Configuration Area SD Host Controller Configuration Area Reserved for Configuration Area Reserved for Configuration Area SD Control Register (BASE Address Register of SD Host Controller Configuration Register --configurable in Offset10h--)
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.12
TC6387XB Specification
Rev. 1.0 02/02/06
- SD Control Register Area As for accessing Resource in SD Control Register Area, use Configuration Register Base Address Reg.(Config.offset: 10h) in SD Host Controller for mapping the settings to access designated Memory Areas (800-FFFh). SD Host Controller Configuration Registers
Offset 10 h
Host Memory Space
Offset Base Address + 000 h
Base Address
SD Control Register : :
Base Address + 1FF h
:
FFh
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.13
TC6387XB Specification
Rev. 1.0 02/02/06
4.3
Register Map TC6387XB holds internal registers for SD Host Controller. SD Host Controller Configuration Register SD Control Register
4.3.1 31
SD Host Controller Configuration Register 23 Reserved 2 Reserved 3 Reserved 5 Reserved 6 SD Control Register Base Address 15 07 Reserved 1 Command Reserved 4 00 Port 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h-2Bh 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h-7Fh 80h 84h 88h 8C-EFh F0h F4h F8h FCh
Reserved 8
Reserved 7 Reserved 9 Interrupt Pin Reserved 10 Gated Clock Control Stop Clock Control Pin Status Power Control2 Power Control1 Reserved 11 Card Detect Mode SD Slot Reserved 12 Reserved 13
Clock Mode Power Control3
Reserved 16 Reserved 19 Reserved 18
Reserved 15 Reserved 17 Reserved 20 Extend Gated Clock Control2 Reserved 23 Extend Gated Clock Control3 Reserved 27
Reserved 14
Reserved 21 Reserved 24 SDLED Enable 1 Reserved 28 SDLED Enable 2
Extend Gated Clock Control1 Reserved 22 Reserved 25 Reserved 26
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.14
TC6387XB Specification
Rev. 1.0 02/02/06
4.3.2
SD Control Register
Base Address: SD Control Register Base Address (Conf.10h) Offset 002h 006h 00Ah 00Eh 012h 016h 01Ah 01Eh 022h 026h 02Ah 02Eh 032h 036h 03Ah 03Eh 0E2h 0E6h 0EAh 0EEh 0F2h 0F6h 0FAh 0FEh 102h 106h 10Ah 10Eh 112h 116h 11Ah 11Eh 122h 126h 12Ah 12Eh 132h 136h 13Ah 13Eh 1E2h 1E6h 1EAh 1EEh 1F2h 1F6h 1FAh 1FEh 15-08 bit 07-00 bit SD Control Reserved 1 Argument1 Transfer Sector Count Response1 Response3 Response5 Response7 SD Buffer Control & Error Status SD Interrupt Mask1 SD Memory Card Transfer Data Length --SD Error Detail Status 1 --------SD Control Reserved 2 SD Control Reserved 3 ------SD Control Reserved 4 SD Control Reserved 6 SD Control Reserved 8 SD Card Port Selection Argument1 Transfer Block Count Response1 Response3 Response5 Response7 SD Buffer Control & Error Status SD Interrupt Mask1 SDIO Card Transfer Data Length --SD Error Detail Status1 --Card Interrupt Control SDIO Host Information SDLED Control SD Control Reserved 9 --------------Offset 000h 004h 008h 00Ch 010h 014h 018h 01Ch 020h 024h 028h 02Ch 030h 034h 038h 03Ch 0E0h 0E4h 0E8h 0ECh 0F0h 0F4h 0F8h 0FCh 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h 128h 12Ch 130h 134h 138h 13Ch 1E0h 1E4h 1E8h 1ECh 1F0h 1F4h 1F8h 1FCh 15-08 bit 07-00 bit SD Command Argument0 Stop internal action Response0 Response2 Response4 Response6 SD Card Status SD Interrupt Mask0 SD Card Clock Control SD Memory Card Option Setup SD Error Detail Status 0 SD Data Port Transaction Control ----SD Software Reset ----------SD Control Reserved 5 SD Control Reserved 7 SD Command Argument0 --Response0 Response2 Response4 Response6 SD Card Status SD Interrupt Mask0 --SDIO Card Option Setup SD Error Detail Status0 SD Data Port Transaction Control Clock & Wait Control Error Control SD Software Reset ------SD Control Reserved 10 -------
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.15
TC6387XB Specification
Rev. 1.0 02/02/06
4.4
Clock/Reset
4.4.1 Clock TC6387XB holds the following two Input Clock Pins: HCLK, CLK32 (1) HCLK : System Clock Input (33MHz Max.). Basic Clock for System Interface and internal operations. Clock Input for 32KHz. The interrupt signal, implied for a SD card insertion and detachment, shall be generated synchronous to this signal. In addition, this signal is base clock, which input to a register which set timeout error time on SD data from a SDIO card.
(2) CLK32 :
4.4.2 Reset-related items - #PCLR: Reset Signal is asserted when power is supplied. All registers(built into TC6387XB) are cleared by #PCLR.
Be sure to deactivate assertion of #PCLR when power supply and HCLK oscillation (better than 1ms) are fairly stable.
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.16
TC6387XB Specification
Rev. 1.0 02/02/06
4.5
Interruption
When the TC6387XB detects the each interrupt sources, TC6387XB asserts interrupt signals (#HINT). It is necessary that the interrupt mask bits are released. This mask bits releasing is controlled by setting SD Interrupt Mask Register(Offset:020-023h, 120-123h). Each factor of the interrupt can be evaluated by referring to SD Card Status Register(Offset:01C-01Dh, 11C-11Dh) or SD Buffer Control & Error Status Register(Offset:01E-01Fh, 11E-11Fh). The details of each factor are listed below.
4.5.1 SD card insertion interrupt by #SDCD + Interrupt Assert Condition When an SD card is inserted to a slot, #SDCD is lowered. This condition causes an interrupt to be generated. #SDCD is not recognized as being lowered unless it remains in "0" state for the number of HCLK cycles specified by CDM[1:0] of Card Detect Mode Register(Config Offset:4Ch). The interrupt is asserted in th timing of raising of CLK32 from #SDCD low state.
HCLK
CDM
CLK32 #SDCD #HINT
+ Factor Evaluation Method The SCIN bit(D4) of SD Card Status Register(Offset:01C-01Dh) is set to "1". +De-asserting Method (1) "0" is written into the SCIN bit(D4) of SD Card Status Register(Offset:01C-01Dh). (2) "1" is written into the MCIN bit(D4) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h).
4.5.2 SD card removal interrupt by #SDCD + Interrupt Assert Condition When an SD card in a slot is removed, #SDCD is raised. This condition causes an interrupt to be generated. After #SDCD is high, the interrupt is asserted in th timing of raising of CLK32.
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.17
TC6387XB Specification
Rev. 1.0 02/02/06
HCLK CLK32 #SDCD #HINT
+ Factor Evaluation Method The SCOT bit(D3) of SD Card Status Register(Offset:01C-01Dh) is set to "1". +De-asserting Method (1) "0" is written into the SCOT bit(D3) of SD Card Status Register(Offset:01C-01Dh). (2) "1" is written into the MCOT bit(D3) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h).
4.5.3 Buffer write enable interrupt + Interrupt Assert Condition When data to be transmitted to the card becomes available for the internal buffer, SD Data Port Register(Offset:030-031h, 130-131h), to be written for a write command, an interrupt is generated.
HCLK SDCLK SDCD3-0 #HINT
Write Data Write is enabled when the data is transferred from the internal buffer to the data transmission circuit. CRC16
+ Factor Evaluation Method In the case of SD memory Card, the SBWE bit(D9) of SD Buffer Control & Error Status Register(Offset:01E01Fh) is set to "1". In the case of SDIO Card, the SBWE bit(D9) of SD Buffer Control & Error Status Register(Offset:11E-11Fh) is set to "1".
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.18
TC6387XB Specification
Rev. 1.0 02/02/06
+De-asserting Method SD memory Card (1) "0" is written into the SBWE bit(D9) of SD Buffer Control & Error Status Register(Offset:01E-01Fh). (2) "1" is written into the MBWE bit(D25) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h). SDIO Card (1) "0" is written into the SBWE bit(D9) of SD Buffer Control & Error Status Register(Offset:11E-11Fh). (2) "1" is written into the MBWE bit(D25) of SD Interrupt Mask Register(Offset:120-123h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
4.5.4 Buffer read enable interrupt + Interrupt Assert Condition When one block of data from the card is stored fully into the internal buffer for a read command, an interrupt is generated. HCLK SDCLK SDCD3-0 #HINT
Read Data CRC16
+ Factor Evaluation Method In the case of SD memory Card, the SBRE bit(D8) of SD Buffer Control & Error Status Register(Offset:01E01Fh) is set to "1". In the case of SDIO Card, the SBRE bit(D8) of SD Buffer Control & Error Status Register(Offset:11E-11Fh) is set to "1". +De-asserting Method SD memory Card (1) "0" is written into the SBRE bit(D8) of SD Buffer Control & Error Status Register(Offset:01E-01Fh). (2) "1" is written into the MBRE bit(D24) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h). SDIO Card (5) "0" is written into the SBRE bit(D8) of SD Buffer Control & Error Status Register(Offset:11E-11Fh). (6) "1" is written into the MBRE bit(D24) of SD Interrupt Mask Register(Offset:120-123h). (7) Hardware reset by #PCLR = "0". (8) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h). TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.19
TC6387XB Specification
Rev. 1.0 02/02/06
4.5.5 Response end interrupt + Interrupt Assert Condition After a response received from an SD card, an interrupt is generated. Regarding R1b response type, after busy released from an SD card, an interrupt is generated. HCLK SDCLK SDCMD #HINT
End bit

HCLK SDCLK SDCMD SDCD0 #HINT
End bit
+ Factor Evaluation Method In the case of SD memory Card, the SREP bit(D0) of SD Card Status Register(Offset:01C-01Dh) is set to "1". In the case of SDIO Card, the SREP bit(D0) of SD Card Status Register(Offset:11C-11Dh) is set to "1". +De-asserting Method SD memory Card (1) "0" is written into the SREP bit(D0) of SD Card Status Register(Offset:01C-01Dh). (2) "1" is written into the MREP bit(D0) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h). SDIO Card (1) "0" is written into the SREP bit(D0) of SD Card Status Register(Offset:11C-11Dh) (2) "1" is written into the MREP bit(D0) of SD Interrupt Mask Register(Offset:120-123h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.20
TC6387XB Specification
Rev. 1.0 02/02/06
4.5.6 R/W end interrupt + Interrupt Assert Condition When read or write processing for an SD card is completed, an interrupt is generated.
HCLK SDCLK SDCD3-0 #HINT Data CRC End
HCLK SDCLK SDCMD SDCD0 #HINT End bit of Write CRC Status
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.21
TC6387XB Specification
Rev. 1.0 02/02/06
+ Factor Evaluation Method In the case of SD memory Card, the SRWA bit(D2) of SD Card Status Register(Offset:01C-01Dh) is set to "1". In the case of SDIO Card, the SRWA bit(D2) of SD Card Status Register(Offset:11C-11Dh) is set to "1". +De-asserting Method SD memory Card (1) "0" is written into the SRWA bit(D2) of SD Card Status Register(Offset:01C-01Dh). (2) "1" is written into the MRWA bit(D2) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h). SDIO Card (1) "0" is written into the SRWA bit(D2) of SD Card Status Register(Offset:11C-11Dh) (2) "1" is written into the MRWA bit(D2) of SD Interrupt Mask Register(Offset:120-123h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
4.5.7 Illegal access error interrupt + Interrupt Assert Condition When an incorrect command index is written into SD Command Register(Offset:000-001h, 100-101h), an interrupt is generated. Each of the following cases is recognized as an incorrect index. (3) is only applying to SD memory Card. (1) SD Command Register is written before the previously issued command is not completed. (2) Though the REP2-0 bits(D10-8) are set to 011b(no response), the NTDT bit(D11) is set to 1b(with data). (3) Though the CMD1-0 bits(D7-6) are set to 00b and the CIX bits(D5-0) are set to 001100b(CMD12), the NTDT bit(D11) is set to 1b(with data).
HCLK SDCLK HA[7-0] #HWE #HINT
0x00
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.22
TC6387XB Specification
Rev. 1.0 02/02/06
+ Factor Evaluation Method In the case of SD memory Card, the ILA bit(D15) of SD Buffer Control & Error Status Register(Offset:01E-01Fh) is set to "1". In the case of SDIO Card, the ILA bit(D15) of SD Buffer Control & Error Status Register(Offset:11E11Fh) is set to "1". +De-asserting Method SD memory Card (1) "0" is written into the ILA bit(D15) of SD Buffer Control & Error Status Register(Offset:01E-01Fh). (2) "1" is written into the IMSK bit(D31) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h). SDIO Card (1) "0" is written into the ILA bit(D15) of SD Buffer Control & Error Status Register(Offset:11E-11Fh). (2) "1" is written into the IMSK bit(D31) of SD Interrupt Mask Register(Offset:120-123h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
4.5.8 Buffer underflow error interrupt + Interrupt Assert Condition If the host reads SD Data Port Register when the data buffer is empty, an interrupt is generated. HCLK SDCL HA[7-0] #HRE #HINT
0x30
+ Factor Evaluation Method In the case of SD memory Card, the SFUF bit(D5) of SD Buffer Control & Error Status Register(Offset:01E-01Fh) is set to "1". In the case of SDIO Card, the SFUF bit(D5) of SD Buffer Control & Error Status Register(Offset: 11E-11Fh) is set to "1".
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.23
TC6387XB Specification
Rev. 1.0 02/02/06
+De-asserting Method SD memory Card (1) "0" is written into the SFUF bit(D5) of SD Buffer Control & Error Status Register(Offset:01E-01Fh). (2) "1" is written into the MFUF bit(D21) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h). SDIO Card (1) "0" is written into the SFUF bit(D5) of SD Buffer Control & Error Status Register(Offset:11E-11Fh). (2) "1" is written into the MFUF bit(D21) of SD Interrupt Mask Register(Offset:120-123h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
4.5.9 Buffer overflow error interrupt + Interrupt Assert Condition If the host writes SD Data Port Register when the data buffer is full, an interrupt is generated.
HCLK SDCLK HA[7-0] #HWE #HINT
0x30
+ Factor Evaluation Method In the case of SD memory Card, the SFOF bit(D4) of SD Buffer Control & Error Status Register(Offset:01E-01Fh) is set to "1". In the case of SDIO Card, the SFOF bit(D4) of SD Buffer Control & Error Status Register(Offset: 11E-11Fh) is set to "1". +De-asserting Method SD memory Card (1) "0" is written into the SFOF bit(D4) of SD Buffer Control & Error Status Register(Offset:01E-01Fh). (2) "1" is written into the MFOF bit(D20) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h).
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.24
TC6387XB Specification
Rev. 1.0 02/02/06
SDIO Card (1) "0" is written into the SFOF bit(D4) of SD Buffer Control & Error Status Register(Offset:11E-11Fh). (2) "1" is written into the MFOF bit(D20) of SD Interrupt Mask Register(Offset:120-123h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
4.5.10 Time out error(command) interrupt + Interrupt Assert Condition If the start bit of a response is not received within SDCLK period X 640(SD memory Card) or X 64(SDIO Card) after the end bit of a command is transmitted to the card, this condition is considered a time out error and an interrupt is generated. HCLK SDCLK
1 2
SDCMD #HINT
640(SD memory) 64(SDIO)
+ Factor Evaluation Method In the case of SD memory Card, the SCTO bit(D6) of SD Buffer Control & Error Status Register(Offset:01E01Fh) and the NCR bit(D16) of SD Error Detail Status Register(Offset:02C-02Fh) are set to "1". However, if a response for automatically issued CMD12 is not received, the NRS bit(D17) is set to "1" for differentiation. In the case of SDIO Card, the SCTO bit(D6) of SD Buffer Control & Error Status Register(Offset:11E-11Fh) and the NCR bit(D16) of SD Error Detail Status Register(Offset:12C-12Fh) are set to "1". +De-asserting Method SD memory Card (1) "0" is written into the SCTO bit(D6) of SD Buffer Control & Error Status Register(Offset:01E-01Fh). (2) "1" is written into the MCTO bit(D22) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h). SDIO Card (1) "0" is written into the SCTO bit(D6) of SD Buffer Control & Error Status Register(Offset:11E-11Fh). (2) "1" is written into the MCTO bit(D22) of SD Interrupt Mask Register(Offset:120-123h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.25
TC6387XB Specification
Rev. 1.0 02/02/06
4.5.11 Read data time out error interrupt + Interrupt Assert Condition If the start bit of data is not detected within the specified period after the end bit of a response for each read command, an interrupt is generated. In the case of SD memory Card, the specified period is set in RTO[3:0] of SD Memory Card Option Setup Register(Offset:028h) in the form of a multiple number of the SDCLK period. In the case of SDIO Card, the specified period is set in TO[3:0] of SD Memory Card Option Setup Register(Offset:128h) in the form of a multiple number of the CLK32 period. Read data time out error is classified into between a command and a read data, and between a read data and a read data in a multiple block transfer. *Between a command and a read data, time out
HCLK SDCLK SDCMD Setting time in SDCD0 #HINT RTO3-0 bits
HCLK SDCLK CLK32 Setting time in TO3-0 bits SDCMD SDCD0 #HINT
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.26
TC6387XB Specification
Rev. 1.0 02/02/06
*Between a read data and a read data, time out
HCLK SDCLK SDCD3-0 #HINT Data CRC End Start
Setting time in RTO3-0 bits
HCLK SDCLK CLK32 SDCD3-0 #HINT Data CRC End Setting time in TO3-0 bits Start
+ Factor Evaluation Method In the case of SD memory Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:01E01Fh) and the NRCS bit(D20) of SD Error Detail Status Register(Offset:02C-02Fh) are set to "1". In the case of SDIO Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:11E-11Fh) and the NRCS bit(D20) of SD Error Detail Status Register(Offset:12C-12Fh) are set to "1". +De-asserting Method SD memory Card (1) "0" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:01E-01Fh). (2) "1" is written into the MDTO bit(D19) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h). SDIO Card (1) "0" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:11E-11Fh). (2) "1" is written into the MDTO bit(D19) of SD Interrupt Mask Register(Offset:120-123h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.27
TC6387XB Specification
Rev. 1.0 02/02/06
4.5.12 Busy time out error interrupt + Interrupt Assert Condition If a busy declaration from the card (DAT0 = "0" after response end) remains longer than the specified time, this condition is considered as a time out error and an interrupt is generated. In the case of SD memory Card, the specified period is set in RTO[3:0] of SD Memory Card Option Setup Register(Offset:028h) in the form of a multiple number of the SDCLK period. In the case of SDIO Card, the specified period is set in TO[3:0] of SD Memory Card Option Setup Register(Offset:128h) in the form of a multiple number of the CLK32 period.
HCLK SDCLK SDCMD Setting time in SDCD0 #HINT RTO3-0 bits
HCLK SDCLK CLK32 SDCMD Setting time in SDCD0 #HINT TO3-0 bits
+ Factor Evaluation Method In the case of SD memory Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:01E01Fh) and the NRCS bit(D20) of SD Error Detail Status Register(Offset:02C-02Fh) are set to "1". In the case of SDIO Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:11E-11Fh) and the NRCS bit(D20) of SD Error Detail Status Register(Offset:12C-12Fh) are set to "1".
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.28
TC6387XB Specification
Rev. 1.0 02/02/06
+De-asserting Method SD memory Card (1) "0" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:01E-01Fh). (2) "1" is written into the MDTO bit(D19) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h). SDIO Card (1) "0" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:11E-11Fh). (2) "1" is written into the MDTO bit(D19) of SD Interrupt Mask Register(Offset:120-123h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
4.5.13 CRC status busy time out error interrupt + Interrupt Assert Condition If a busy declaration from the card (DAT0 = "0" after Write CRC Status) remains longer than the specified time, this condition is considered as a time out error and an interrupt is generated. In the case of SD memory Card, the specified period is set in RTO[3:0] of SD Memory Card Option Setup Register(Offset:028h) in the form of a multiple number of the SDCLK period. In the case of SDIO Card, the specified period is set in TO[3:0] of SD Memory Card Option Setup Register(Offset:128h) in the form of a multiple number of the CLK32 period.
HCLK SDCLK SDCMD SDCD0 #HINT End bit of Write CRC Status
Setting time in RTO3-0 bits
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.29
TC6387XB Specification
Rev. 1.0 02/02/06

HCLK SDCLK CLK32 SDCMD Setting time in TO3-0 bits SDCD0 #HINT End bit of Write CRC Status + Factor Evaluation Method In the case of SD memory Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:01E01Fh) and the KBSY bit(D22) of SD Error Detail Status Register(Offset:02C-02Fh) are set to "1". In the case of SDIO Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:11E-11Fh) and the KBSY bit(D22) of SD Error Detail Status Register(Offset:12C-12Fh) are set to "1". +De-asserting Method SD memory Card (1) "0" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:01E-01Fh). (2) "1" is written into the MDTO bit(D19) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h). SDIO Card (1) "0" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:11E-11Fh). (2) "1" is written into the MDTO bit(D19) of SD Interrupt Mask Register(Offset:120-123h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.30
TC6387XB Specification
Rev. 1.0 02/02/06
4.5.14 CRC status time out error interrupt + Interrupt Assert Condition If the start bit of CRC status is not detected within the specified period after the end bit of block data for a write command, an interrupt is generated. In the case of SD memory Card, the specified period is set in RTO[3:0] of SD Memory Card Option Setup Register(Offset:028h) in the form of a multiple number of the SDCLK period. In the case of SDIO Card, the specified period is set in TO[3:0] of SD Memory Card Option Setup Register(Offset:128h) in the form of a multiple number of the CLK32 period.
HCLK SDCLK Write CRC Status SDCD0 Setting time in #HINT RTO3-0 bits

HCLK SDCLK CLK32 Write CRC Status SDCD0 Setting time in #HINT TO3-0 bits
+ Factor Evaluation Method In the case of SD memory Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:01E01Fh) and the NWCS bit(D21) of SD Error Detail Status Register(Offset:02C-02Fh) are set to "1". In the case of SDIO Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:11E-11Fh) and the NWCS bit(D21) of SD Error Detail Status Register(Offset:12C-12Fh) are set to "1".
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.31
TC6387XB Specification
Rev. 1.0 02/02/06
+De-asserting Method SD memory Card (1) "0" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:01E-01Fh). (2) "1" is written into the MDTO bit(D19) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h). SDIO Card (1) "0" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:11E-11Fh). (2) "1" is written into the MDTO bit(D19) of SD Interrupt Mask Register(Offset:120-123h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.32
TC6387XB Specification
Rev. 1.0 02/02/06
4.5.15 End bit error interrupt + Interrupt Assert Condition If a bit that should be the end bit for the response, read data or CRC status received from the card is "0", an interrupt for detecting an incorrect end bit is generated.
HCLK SDCLK SDCMD #HINT
End bit
+ Factor Evaluation Method In the case of SD memory Card, the SEND bit(D2) of SD Buffer Control & Error Status Register(Offset:01E01Fh) and the WEBER bit, REBER bit, SEBER bit and CEBER bit(D5-2) of SD Error Detail Status Register(Offset:02C-02Fh) are set to "1". In the case of SDIO Card, the SEND bit(D2) of SD Buffer Control & Error Status Register(Offset:11E-11Fh) and the WEBER bit, REBER bit and CEBER bit(D5-4,2) of SD Error Detail Status Register(Offset:12C-12Fh) are set to "1". Bit 5 4 3 2 Name WEBER REBER SEBER CEBER Error factor End bit error for Write CRC status End bit error for read data End bit error of a response for automatically issued CMD12 End bit error for a response (other than SEBER ) Notes
Only SD memory Card
+De-asserting Method SD memory Card (1) "0" is written into the SEND bit(D2) of SD Buffer Control & Error Status Register(Offset:01E-01Fh). (2) "1" is written into the MEND bit(D18) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h). SDIO Card (1) "0" is written into the SEND bit(D2) of SD Buffer Control & Error Status Register(Offset:11E-11Fh). (2) "1" is written into the MEND bit(D18) of SD Interrupt Mask Register(Offset:120-123h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.33
TC6387XB Specification
Rev. 1.0 02/02/06
4.5.16 CRC error interrupt + Interrupt Assert Condition If the CRC value for the response, read data or CRC status received from the card does not agree with the value internally calculated by TC6387XB, an interrupt is generated
HCLK SDCLK SDCMD SDCD3-0 #HINT
End bit
+ Factor Evaluation Method In the case of SD memory Card, the SCRC bit(D1) of SD Buffer Control & Error Status Register(Offset:01E01Fh) and the WCRCE bit, RCRCE bit, SCRCE bit and CCRCE bit(D11-8) of SD Error Detail Status Register(Offset:02C-02Fh) are set to "1". In the case of SDIO Card, the SCRC bit(D1) of SD Buffer Control & Error Status Register(Offset:11E-11Fh) and the WCRCE bit, RCRCE bit and CCRCE bit(D11-10,8) of SD Error Detail Status Register(Offset:12C-12Fh) are set to "1". Bit 11 10 9 8 Name WCRCE RCRCE SCRCE CCRCE Error factor Write CRC status error for a write command CRC error for read data CRC error of a response for automatically issued CMD12 CRC error for a response (other than SCRCE) Notes
Only SD memory Card
+De-asserting Method SD memory Card (1) "0" is written into the SCRC bit(D1) of SD Buffer Control & Error Status Register(Offset:01E-01Fh). (2) "1" is written into the MCRC bit(D17) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h). SDIO Card (1) "0" is written into the SCRC bit(D1) of SD Buffer Control & Error Status Register(Offset:11E-11Fh). (2) "1" is written into the MCRC bit(D17) of SD Interrupt Mask Register(Offset:120-123h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.34
TC6387XB Specification
Rev. 1.0 02/02/06
4.5.17 Command Index error interrupt + Interrupt Assert Condition If the command index portion of the response received from the card does not agree with the index issued just before, an interrupt is generated.
HCLK SDCLK
Abnormal SDCMD command index
End bit
#HINT
+ Factor Evaluation Method In the case of SD memory Card, the SCIX bit(D0) of SD Buffer Control & Error Status Register(Offset:01E01Fh) and the RCMDE bit(D0) of SD Error Detail Status Register(Offset:02C-02Fh) are set to "1". If a response for automatically issued CMD12 is not normal, "1" is set to the SCMDE bit(D0). In the case of SDIO Card, the SCIX bit(D0) of SD Buffer Control & Error Status Register(Offset:11E-11Fh) and the RCMDE bit(D0) of SD Error Detail Status Register(Offset:12C-12Fh) are set to "1". +De-asserting Method SD memory Card (1) "0" is written into the SCIX bit(D0) of SD Buffer Control & Error Status Register(Offset:01E-01Fh). (2) "1" is written into the MCIX bit(D16) of SD Interrupt Mask Register(Offset:020-023h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0E0h). SDIO Card (1) "0" is written into the SCIX bit(D0) of SD Buffer Control & Error Status Register(Offset:11E-11Fh). (2) "1" is written into the MCIX bit(D16) of SD Interrupt Mask Register(Offset:120-123h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.35
TC6387XB Specification
Rev. 1.0 02/02/06
4.5.18 Illegal function select interrupt + Interrupt Assert Condition Although a transaction is remaining on the SD bus, or a state of SD controller is acceptable, other function in SDIO Card is selected by SD host controller, then an interrupt is generated. HCLK SDCLK HA[7-0] #HWE SDCD3-0 #HINT
Write data or Read data 0x00
HCLK SDCLK HA[7-0] #HWE SDCD3-0 #HINT
0x00
+ Factor Evaluation Method The ILFSL bit(D13) of SD Buffer Control & Error Status Register(Offset:11E-11Fh) is set to "1". +De-asserting Method (1) "0" is written into the ILFSL bit(D13) of SD Buffer Control & Error Status Register(Offset:11E-11Fh). (2) "1" is written into the IFSMSK bit(D29) of SD Interrupt Mask Register(Offset:120-123h). (3) Hardware reset by #PCLR = "0". (4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1E0h).
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.36
TC6387XB Specification
Rev. 1.0 02/02/06
4.5.19 SDIO Card interrupt + Interrupt Assert Condition When an interrupt from SDIO Card by using SDCD1 signal is detected, an interrupt is generated. Please release the interrupt mask by the CIMSK0 bit(D8) of Card Interrupt Control Register(Offset:136h), so the interrupt from #HINT would be generated.
HCLK SDCLK SDCD1 #HINT
+ Factor Evaluation Method The CINT0 bit(D12) of Card Interrupt Control Register(Offset:136h) is set to "1". +De-asserting Method (1) "0" is written into the CINT0 bit(D12) of Card Interrupt Control Register(Offset:136h). (2) "1" is written into the CIMSK0 bit(D8) of Card Interrupt Control Register(Offset:136h). (3) Hardware reset by #PCLR = "0".
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.37
TC6387XB Specification
Rev. 1.0 02/02/06
4.6
Card Slot Power Supply Control TC6387XB is designed to provide connection with MIC2563(Power Supply Control LSI).The following suggests applicable circuits:
System Power Supply 3.3V Vcc
TC6387XB
SDPWR
VC3EN VC5EN EN0 EN1 VC3EN VC5EN EN0 EN1 MIC2563 GND
SDVCC (3.3v) SD Card Slot
4.6.1
SD Card Slot Power Supply Controller
Power supply for SD Card is controlled by configuring Power Control Register 2(Config Offset 49h) after detecting SD Card insertion. When #SUSPEND is asserted to low, power supply for SD Card can be automatically shut out by configuring Power Control Register 3(Config Offset 4Ah). Parallel Power Supply Control Signals Function/Remarks SD Card Slot Power Supply Controller. 3.3V Enable Signal
Signal Name SDPWR
Pin B1
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.38
TC6387XB Specification
Rev. 1.0 02/02/06
4.7
SDLED signal TC6387XB has the SDLED signal for SD interface. This signal is controlled by setting SDLED Control Register(Offset:13Eh). Before accessing SDLED Control Register(Offset:13Eh), please set following registers. *Set SDLED Enable Register 1(Config Offset:FAh) to 12h. *Set SDLED Enable Register 2(Config Offset:FEh) to 80h.
4.8
Clock supply to SD Card
The SDCLK signal is used for a provision of SD Memory Card or SDIO Card. Please refer to the following setting for enabling the SDCLK output. (1) Set Stop Clock Control Register (Config Offset:40h) to 1Fh. (2) Set D0 of SD Software Reset Register (Offset:0E0h) to 1b. (3) Set D7-0 of SD Card Clock Control Register (Offset:024h). These bits are used for setting the frequency of SDCLK. 80h : SDCLK=HCLK/512 40h : SDCLK=HCLK/256 20h : SDCLK=HCLK/128 10h : SDCLK=HCLK/64 08h : SDCLK=HCLK/32 04h : SDCLK=HCLK/16 02h : SDCLK=HCLK/8 01h : SDCLK=HCLK/4 00h : SDCLK=HCLK/2 In addition, TC6387XB holds a function that SDCLK can have same frequency as HCLK. In this case, D7-0 settings of SD Card Clock Control Register (Offset:024h)becomes invalid setting. * Set D0 of Clock Mode Register (Config Offset:42h) to 1b. * Set D15 of SD Card Clock Control Register (Offset:024h) to 1b. Please attend that the specification of SDCLK is max.25MHz at the case of SD Card and is max.20MHz at the case of MultiMedia Card. (4) D8 of SD Card Clock Control Register (Offset:024h) to 1b. (5) D8 of Clock & Wait Control Register (Offset:138h) to 1b.
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.39
TC6387XB Specification
Rev. 1.0 02/02/06
4.9
Suspension TC6387XB executes buffer-off for Input Signals from Host interface and SD Card by asserting #SUSPEND.
Phase I Phase II Phase III Phase
VCC
#PCLR
X X
#SUSPEND
Register Clear (Internal) HCLK
X
SUSPEND State
* Phase I: * Phase II: * Phase III:
* Phase IV:
Immediately after the power is turned ON, #PCLR indicates "L" whereas #SUSPEND indicates "H". All the circuits are cleared in this state. Assertion of #PCLR deactivated (H). Normal state. Assert #SUSPEND to activate SUSPEND state. TC6387XB executes Anti-Penetration Process for Input Signals in this state. Also, TC6387XB does not accept Host Interface transactions in this state. Moreover, stopping HCLK can reduce the power consumption. TC6387XB is brought back to normal state by deactivating assertion of #SUSPEND.
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.40
TC6387XB Specification
Rev. 1.0 02/02/06
It shows what state each signals are in suspend mode (#SUSPEND=Low).
NAME HD15 HD14 HD13 HD12 HD11 HD10 HD9 HD8 HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 HA11 HA10 HA9 HA8 HA7 HA6 HA5 HA4 HA3 HA2 HA1
Pin H5 F4 G5 F5 H6 G6 H7 H8 G8 F6 F7 E7 F8 E8 D8 E6 D7 D6 C8 C7 B8 A8 A7 C6 B6 B5 A6
IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I I I I I I I I I I I
State Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
NAME #HCS #HOE #HWE #HBEL #HBEH HRDY SDCD3 SDCD2 SDCD1 SDCD0 SDCMD SDCLK #SDCD SDWP SDLED SDPWR HCLK CLK32 #HINT #PCLR #SUSPEND TST2 TST1 TST0 RSV0 RSV1 RSV2
Pin A5 G3 G4 H4 H3 F2 C2 C3 D3 E1 D2 D1 E2 E3 F1 B1 H1 A1 G1 F3 A4 B3 A3 C4 A2 B4 C5
IO I I I I I O (OD) IO IO IO IO IO O I I O O I I O (OD) I I I I I I I I
State Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z L Hi-Z * Hi-Z -
* This signal is not controlled by #SUSPEND signal. The state before suspend mode (#SUSPEND=high) is held.
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.41
TC6387XB Specification
Rev. 1.0 02/02/06
4.10
Pull-up/down Resistance PULL- UP/DOWN Resistance is to be installed for each interface in TC6387XB. Be aware that Resistance Values (described "Res. Val." in the following tables) indicated in the following tables are provided only for references.
4.10.1 NAME HRDY
Host Interface Pin F2 IO O (OD) Pull-up/ Pull-down Pull-up Pull-up Power VCC Res. Val. 10K Ready FUNCTION/REMARKS
4.10.2 NAME SDCD3 SDCD2 SDCD1 SDCD0
SD Card Interface Pin C2 C3 D3 E1 D2 D1 E2 E3 IO Pull-up/ Pull-down Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Power SDVCC SDVCC SDVCC SDVCC SDVCC VCC VCC Res. Val. 47K 100K 100K 100K *1 : 33K *2 : 100K 10K 10K FUNCTION/REMARKS
IO
SD Card Slot /Data Bus
SDCMD SDCLK #SDCD SDWP
IO O I I
SD Card Slot /Command *1 : Support MultiMedia Card *2 : Do not support MultiMedia Card SD Card Slot /Divided HCLK Clock SD Card Slot /Detection SD Card Slot /Write Protection
4.10.3
System Interface Pull-up/ Pull-down Pull-up Pull-up Power VCC
NAME #HINT
Pin G1
IO O (OD)
Res. Val. 10K Interruption
FUNCTION/REMARKS
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.42
TC6387XB Specification
Rev. 1.0 02/02/06
4.11
Connection example of SD Card socket
It is shown that total 10 signal connections example of TC6387XB which have 9 signals of SD card interface and 1 signal of a power supply control for SD card. As for our company, using FPS009-3000 of theYAMAICHI Company did a movement confirmation of the SD card. An outside pull-up/down resistance that is mentioned on an item of the "4.10 Pull-up/down resistance" is not shown in a bottom figure. When you design a circuit, please refer to recommended resistance by an item of the "4.10 Pull-up/down " and a bottom figure.
TC6387XB SDCD3 SDCMD SDCLK SDCD0 SDCD1 SDCD2 SDWP #SDCD SDPWR SDLED MIC2563 manufactured by the MICREL Company DAT3 CMD Vss Vdd FPS009-3000 manufactured CLK by the YAMAICHI Company Vss DAT0 DAT1 DAT2 SD-WP Vss SD-SW
GND
GND
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.43
TC6387XB Specification
Rev. 1.0 02/02/06
5 5.1
Electrical Characteristic Absolute Maximum Standard Absolute Maximum Ratings Symbol Parameter Vcc Supply Voltage Range Vin3 Input Voltage (3.3V) Vout Output Voltage Tstg Storage Temperature Range Note 1: Vcc Power Supply
Min -0.3 -0.3 -0.3 -40
Max 5.0 Vcc+0.3 Vcc+0.3 125
Unit V V V degree C
Condition GND=0V GND=0V GND=0V
Note 1
Note: Absolute Maximum Ratings indicates that stress greater than the values described above might cause permanent damages to the devices and does not guarantee all the performances within Absolute Maximum Ratings 5.2 5.2.1 DC Characteristic Recommended Conditions for proper performances Symbol Vcc Topr Parameter Supply Voltage for Core Logic Ambient Temperature under bias Min 3.0 0 Typ 3.3 25 Max 3.6 70 Unit V degree C Note
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.44
TC6387XB Specification
Rev. 1.0 02/02/06
5.2.2
Host Interface DC Characteristic Host Interface DC Characteristic(Vcc =3.0-3.6V, Ta=0-70degree C) Symbol Vih Vil Iilk Voh Vol Parameter Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Min 0.8Vcc -10 2.4 Max 0.2Vcc 10 0.4 Unit V V uA V V Condition Note 1-1 1-1 1-1 1-2 1-2
0Note1-1: Applied for HD[15-0] ,HA[11-1], #HCS, #HOE, #HWE, #HBEL, #HBEH pins Note1-2: Applied for HD[15-0], HRDY pins
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.45
TC6387XB Specification
Rev. 1.0 02/02/06
5.2.3
SD Card Interface Pin DC Characteristic SD Card Interface DC Characteristic: 3.3V Operation (Vcc =3.0-3.6V, Ta=0-70degree C) Symbol Vih Vil Vih Vil Voh1 Vol1 Voh2 Vol2 Iilk Rdat3 Parameter Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage 1 Output Low Voltage 1 Output High Voltage 2 Output Low Voltage 2 Input Leakage Current Pull-up resistance inside card (pin1) Min 0.7Vcc Vss-0.3 0.8Vcc 0.75Vcc 2.4 -10 10 Max Vcc+0.3 0.175Vcc 0.2Vcc 0.125Vcc 0.4 10 90 Unit V V V V V V V V uA K Condition Note 2-1 2-1 2-2 2-2 2-3 2-3 2-4 2-4 2-1 2-2
Iout=-1mA 3.0VNote2-1 Applied for SDCD[3:0], SDCMD, SDWP pins Note2-2 Applied for #SDCD pin Note2-3 Applied for SDCD[3:0], SDCMD, SDCLK pins Note2-4 Applied for SDLED pin
5.2.4
SD Card Power Supply Control DC Characteristic SD Card Power Supply Control DC Characteristic: 3.3V Operation (Vcc =3.0-3.6V, Ta=0-70degree C) Symbol Voh Vol Parameter Output High Voltage Output Low Voltage Min 2.4 Max 0.6 Unit V V Condition Iout=-100uA 3.0VNote2-5 Applied for SDPWR pin
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.46
TC6387XB Specification
Rev. 1.0 02/02/06
5.2.5
System Interface Pin DC Characteristic System Interface Pin DC Characteristic (VCC =3.0-3.6V, Ta=0-70degree C) Symbol Vih Vil Iilk Voh Vol Parameter Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Min 0.8Vcc -10 2.4 Max 0.2Vcc 10 0.4 Unit V V uA V V Test Condition Note 3-1 3-1 3-1 3-2 3-2
0Note3-1 Applied for HCLK, CLK32, #PCLR, #SUSPEND pins Note3-2 Applied for #HINT pin
5.2.6
TEST Pin DC Characteristic TEST Pin DC Characteristic (Vcc =3.0-3.6V, Ta=0-70degree C) Symbol Vih Vil Iilk Parameter Input High Voltage Input Low Voltage Input Leakage Current Min 0.8Vcc -10 Max 0.2Vcc 10 Unit V V A Condition Note 4-1 4-1 4-1
0Note4-1 Applied for TST[2:0] pins
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.47
TC6387XB Specification
Rev. 1.0 02/02/06
5.2.7
Power Consumption Characteristic
Power Supply Current Symbol Parameter Iccstd 1 Power Supply Current, Standby
Min
Typ
Max
Unit uA
Iccstd 2
Power Supply Current, Standby
IccSD/M MC
Power Supply Current, Operating SD Card or MultiMedia Card
T.B.D
uA
mA
Condition HCLK=0, CLK32=0 VCC=3.6V #SUSPEND=low HCLK=0, CLK32=32KHz VCC=3.6V #SUSPEND=low HCLK=33MHz, CLK32=32KHz VCC=3.6V
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.48
TC6387XB Specification
Rev. 1.0 02/02/06
5.3 5.3.1
AC Characteristic Host Interface Signal AC Characteristic
(1)System Clock AC Characteristic (Vcc=3.0-3.6V, Ta=0-70degree C) Symbol Parameter HCLK Tcyc CLK cycle time Thigh CLK High time Tlow CLK Low time t1d HCLK Rising Time t1e HCLK Falling Time
Min 30 10 10 -
Max
Unit ns ns ns ns ns
Notes
5 5
HCLK Timing
Tcyc Tlow
HCLK
Thigh 0.8VCC t1d 0.2VCC
t1e
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.49
TC6387XB Specification
Rev. 1.0 02/02/06
(2)#PCLR Reset AC Characteristic (Vcc=3.0-3.6V, Ta=0-70degree C) Symbol Trst Trst-clk Parameter #PCLR Reset active time after power stable Reset active time after CLK stable Min 1 1 Max Unit ms ms Notes
#PCLR Reset Timing
POWER
0.8Vcc
#PCLR
Trst
0.8Vcc
Trst-clk
0.2Vcc 0.8Vcc
HCLK
0.2Vcc
#PCLR Reset Timing
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.50
TC6387XB Specification
Rev. 1.0 02/02/06
(3)Standard Memory Interface Signal AC Characteristic
(Vcc=3.0-3.6V,Ta=0-70degree C) Symbol thos1 thos2 thos3 thos4 tpd0 thoh1 thoh2 thoh3 twh1 twh2 twl1 twl2 tos1 tpdh1 t1 t2 tw1 tw2 Parameter Address setup to #HCS #HCS, #HBEL, #HBEH setup to #HOE or #HWE Address setup to #HOE or #HWE low Address setup to #HOE or #HWE low Data delay time after #HWE low Data hold after #HWE high #HCS, #HBEL, #HBEH hold asserted after #HOE or #HWE de-asserted Address Hold after #HOE or #HWE de-asserted #HOE high time #HWE high time #HOE low time #HWE low time Data Setup for HRDY Release #HOE,HD[15:0] hold time #HOE low to HRDY low time #HWE low to HRDY low time HRDY low time HRDY low time Min 0 20 20 20 5 10 5 3HCLK 3HCLK 3HCLK 3HCLK 1HCLK 5 15 15 1HCLK 1HCLK Max 1HCLK Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes
*1 *1
*1 There are two ways to have wait modes. A. External wait mode method(ie. not to use CPU generated wait time): Please input #HOE/#HWE signal using pulse width of 3HCLK minimum. If this has been applied, HRDY of TC6380AF signal will be activated and read/write cycle will be extended to access registers. By this method, read/write access cycle will become 16HCLK maximum.
B. Internal wait mode method(ie. use CPU generated wait time): Please input #HOE/#HWE signal using enough pulse width, which should be 16HCLK minimum. If this has been applied, HRDY signal is not necessary for TC6380AF register read/write operations.
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.51
TC6387XB Specification
Rev. 1.0 02/02/06
thos1
#HCS HA[11:1] #HBEL, #HBEH #HOE
thos2 thos3 A0 twl1 t1 thoh3 twh1
tw1 tos1
thoh2 thos4 A0+2
HRDY
HD[15:0]
D0
tpdh1
D1
thos1 thos2
#HCS HA[11:1] #HBEL, #HBEH #HWE
thoh2 thos4 A0 twl2 A0+2 thoh3 twh2
thos3
t2
HRDY
tw2
tpd0
HD[15:0]
thoh1 D0 D1
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.52
TC6387XB Specification
Rev. 1.0 02/02/06
5.3.2
SD Card Interface Signal AC Characteristic (Vcc=3.0-3.6V, Ta=0-70degree C)
Symbol Fpp Fod Twl Twh Ttlh Tthl Tisu Tih Todly
Parameter SDCD[3:0], SDCMD, SDCLK Clock frequency Data Transfer Mode Clock frequency Identification Mode Clock Low time Clock High time Clock fall time Clock rise time Input set-up time Input hold time Output delay time
Min 0 0 10 10 10 10 -
Max 25 256 10 10 15
Unit MHz KHz ns ns ns ns ns ns ns
Notes Cl=25pF Cl=25pF Cl=25pF Cl=25pF Cl=25pF Cl=25pF Cl=25pF Cl=25pF Cl=25pF
SD Card Interface Signals Timing 0.75Vcc SDCLK (output) 0.125Vcc INPUT Vil=0.25Vcc, OUTPUT Todly Vol=0.125Vcc, Timing for SD Card Interface Signals Voh=0.75Vcc Todly (min) Vih=0.625Vcc Tthl Twl Ttlh Tisu Tih Fpp, Fod Twh
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.53
TC6387XB Specification
Rev. 1.0 02/02/06
5.3.3
System Interface Signal AC Characteristic (Vcc=3.0-3.6V, Ta= 0-70degree C)
CLK32 AC Characteristic (Vcc=3.0-3.6V, Ta=0-70degree C) Symbol Parameter CLK32 Tcyc32 CLK cycle time Thigh32 CLK High time Tlow32 CLK Low time t1d32 CLK32 Rising Time t1e32 CLK32 Falling Time
Min 31 11 11 10 10
Max
Unit us us us ns ns
Notes
-
CLK32 Timing
Tcyc32 Tlow32
CLK32
Thigh32 0.8VCC 0.2VCC
t1e32
t1d32
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.54
TC6387XB Specification
Rev. 1.0 02/02/06
6 6.1
Caution in coding device driver Regarding a SD card insertion and removal If a SD card would be inserted or removed, you should perform software reset with SD Software Reset Register(Offset:0E0h, 1E0h). *In SD card insertion If a SD card would be inserted, you should perform software reset with SD Software Reset Register(Offset:0E0h, 1E0h). Then, you should release software reset and initialize a SD card. *In SD card removal If a SD card would be removed, you should perform software reset with SD Software Reset Register(Offset:0E0h, 1E0h). Afterward, when a SD card would be inserted, you should release software reset and initialize a SD card.
6.2
Regarding controlling Stop Clock Control Register Stop Clock Control Register(Config Offset:40h) is used to control internal clocks of TC6387XB. When you would set this register, you could not set different values between EMCK3 bit(D2) and EMCK1 bit(D0).
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.55
TC6387XB Specification
Rev. 1.0 02/02/06
7
Package outline
A1 pin
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.56
TC6387XB Specification
Rev. 1.0 02/02/06
Appendix A TC6387XB function confirmation with standard memory interface
TOSHIBA connected TC6387XB board to MN1A7T0200 board manufactured the COMPUTEX corporation. Then , TOSHIBA confirmed to the function of SD memory Card and MMC. The following indicates these circuits.
Standard memory interface connection MN1A7T0200 board TC6387XB board SD memory Card CPU ARM7 TC6387XB
A.1
Sample soft for standard memory interface of TC6387XB
TOSHIBA developed the device driver of SD memory Card with above environment. TOSHIBA provide these driver source to you as sample soft of TC6387XB.
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.57
TC6387XB Specification
Rev. 1.0 02/02/06
A.2
Wait mode specification
MN1A7T0200 board and TC6380A board support internal and external wait mode of 32/16/8 bit access. The correspondence list indicates as followings. MN1A7T0200 board 32bit internal wait mode 16bit internal wait mode 8bit internal wait mode 32bit external wait mode 16bit external wait mode 8bit external wait mode *1 Support TC6387XB specification Not support TC6387XB board Not support Notes *1
Support Support Support
Not support Not support
Support Support
Not support
Support
Support Not support *1 *2 *2
Support Support
Support Support
Because TC6387XB supports 16 bit bus interface, TOSHIBA do not confirm this function.
*2 MN1A7T0200 board supports only external wait mode of 32 bit access. When TOSHIBA confirmed to the function of SD memory Card, SDIO Card and SmartMediaTM with external wait mode of 16bit and 8bit access, TOSHIBA deal with these mode by controlling #HCS, #HWE, #HRE, #HBEH, #HBEL, HA[11:1], HD[15:0] and HRDY with using FPGA LSI mounted to TC6387XB board. External wait access of 16 bit and 8 bit were realized by shifting address bits against external wait access of 32 bit from MN1A7T0200 board. These access(*3) can be switched by FPGA register. *3 Internal wait access of 16 bit, external wait access of 16 bit and external wait access of 8 bit.
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.58
TC6387XB Specification
Rev. 1.0 02/02/06
A.3
The wiring image of 16bit internal wait mode
In 16 bit internal wait mode, the connection of MN1A7T0200 board and TC6387XB is as following. MN1A7T0200 board
FNCS[3] FA[23] FA[22] FA[21] FA[20] FNWE[1] FNWE[0] FNRE FA[0] FA[11] FA[10] FA[9] FA[8] FA[7] FA[6] FA[5] FA[4] FA[3] FA[2] FA[1] FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0] FNACK FNMI FNIRQ[0] #HINT 3.3V Open HRDY
TC6387XB board
#HCS
#HWE #HOE #HBEH #HBEL HA11 HA10 HA9 HA8 HA7 HA6 HA5 HA4 HA3 HA2 HA1 HD15 HD14 HD13 HD12 HD11 HD10 HD9 HD8 HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.59
TC6387XB Specification
Rev. 1.0 02/02/06
A.4
The wiring image of 16bit external wait mode
In 16 bit external wait mode, the connection of MN1A7T0200 board and TC6387XB is as following. MN1A7T0200 board access to TC6387XB board with 32 bit. MN1A7T0200 board
FNCS[3] FA[23] FA[22] FA[21] FA[20] FNWE[1] FNWE[0] FNRE FA[1] FA[12] FA[11] FA[10] FA[9] FA[8] FA[7] FA[6] FA[5] FA[4] FA[3] FA[2] FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0]
COUNTER
TC6387XB board
#HCS
#HWE #HOE #HBEH #HBEL HA11 HA10 HA9 HA8 HA7 HA6 HA5 HA4 HA3 HA2 HA1 HD15 HD14 HD13 HD12 HD11 HD10 HD9 HD8 HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 HRDY
CPUCLK 1pulse
FNACK CPUCLK (20MHz)
3.3V FNMI FNIRQ[0] 33MHz #HINT
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.60
TC6387XB Specification
Rev. 1.0 02/02/06
B
Reference diagram
3.3V
3.3V
HD[15:0] HA[11:1] #HBEH #HBEL #HWE HRDY #HOE #HCS
10K
SYSTEM I/F (5pin)
HCLK CLK32 #HINT #PCLR #SUSPEND
HOST I/F (33pin)
10K
3.3V
TST2 TST1 TST0
TEST PIN (3pin)
TC6387XB
Ground (5pin)
RSV2 RSV1 RSV0
Reserved (3pin)
SD Card I/F (9pin)
SDCMD SDCD3 SDCD2 SDCD1 SDCD0 SDCLK #SDCD SDWP SDLED
SD Card Power Control Pin (1pin)
SDPWR
3.3V
SDVCC
100K *
100K
100K
100K
Please check the chapter 4.6 application circuit.
SDVCC
10K
10K
* : Change the resistance value to be 33k in case one uses MMC.
47K
DAT1
DAT3
DAT2
DAT0
CMD
SD-SW
SD-WP
CLK
Vdd
Vss
Vss
SD Card Socket
YAMAICHI-denki FPS009-3000
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.61
Vss
Power (5pin)
TC6387XB Specification
Rev. 1.0 02/02/06
*
TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. The information contained herein is subject to change without notice.
*
*
TOSHIBA CONFIDENTIAL TOTAL 62 PAGE NO.62

▲Up To Search▲

Price & Availability of TC6387XB

	To Download TC6387XB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .